Vector State Machine Definition
A Vector State Machine is a sequence
of logic controlled by a single engine. As such, the elements are ordered
following a strict linear sequence. The Vector State Machine (VSM) can be
viewed as a chip; for example FPGA. Any number of VSMs can be combined to
create an application.
The Vector State Machine containers are implemented as a dynamic array or table; Just as regular arrays, vector containers have their elements stored in contiguous storage locations, which means that their elements can be accessed using a temporal pointer but also using offsets on regular pointers to elements.
Traditional program logic is control flow mixed with data manipulation. This style of program has garnered the term “spaghetti code”. The if-then-else logic (ITE); that is the foundation of spaghetti code; where the results of the “if” logic test modifies data based on whether the logic test is true or false. The control flow is from ITE statement to ITE statement. The temporal component is implicit in this form of logic. The traditional program must maintain overhead logic to track execution as an application executes.
The Vector State Machine application
uses a temporal pointer to control application execution. That is, each Vector
State Machine has only one “if” statement. The temporal pointer replaces the
overhead logic associated with the tradition ITE approach thereby reducing
program size and increasing performance. This temporal pointer approach also
results in a one-to-one mapping of design logic to implemented logic. Several
of this difference have been analyzed and show significant reductions in
Vector State Machines are good at:
Compared to traditional logic, VSMs provide better performance for these tasks, plus they have the ability to be easily modified. Consider that the logic is physically separate from the data. This separation allows an application to be modified or patched more easily; especially for embedded applications.